正交解码及在旋转编码器中的应用

正交解码

modulequad(clk,quadA,quadB,count); inputclk,quadA,quadB; output[7:0]count; regquadA_delayed,quadB_delayed; always@(posedgeclk)quadA_delayed<=quadA; always@(posedgeclk)quadB_delayed<=quadB; wirecount_enable=quadA^quadA_delayed^quadB^quadB_delayed; wirecount_direction=quadA^quadB_delayed; reg[7:0]count; always@(posedgeclk)begin if(count_enable) begin if(count_direction)count<=count+1; elsecount<=count-1; end end endmodule

实际的电路

modulequad(clk,quadA,quadB,count); inputclk,quadA,quadB;output[7:0]count; reg[2:0]quadA_delayed,quadB_delayed; always@(posedgeclk)quadA_delayed<={quadA_delayed[1:0],quadA}; always@(posedgeclk)quadB_delayed<={quadB_delayed[1:0],quadB}; wirecount_enable=quadA_delayed[1]^quadA_delayed[2]^quadB_delayed[1]^quadB_delayed[2]; wirecount_direction=quadA_delayed[1]^quadB_delayed[2]; reg[7:0]count; always@(posedgeclk)begin if(count_enable) begin if(count_direction)count<=count+1;elsecount<=count-1; end end endmodule